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FPT University|e-Resources > Bài báo khoa học (Scientific Articles) > Articles published by FPT lecturers >
Please use this identifier to cite or link to this item: /handle/123456789/2062

Title: High-Level Modeling and Simulation of a Novel Reconfigurable Network-on-Chip Router
Authors: Le Van, Thanh Vu
Tran, Xuan Tu
Keywords: Network-on-Chip
Recon guration
High-level modeling
Issue Date: 31-Dec-2014
Publisher: REV
Abstract: In this paper, we present a novel router architecture for implementing a Reconfigurable Network-on-Chip (RNoC) at high-level design using SystemC. The RNoC is an adaptive NoC-based system-on-chip providing a dynamic reconfigurable communication mechanism. By adding a virtual port–named Routing Modification port–into the conventional router architecture, the network router is able to route communication data flexibly whenever the target routing path is blocked, by unwanted defects or intently by a software programme to ...
Description: 6 pages
URI: http://ds.libol.fpt.edu.vn/handle/123456789/2062
Appears in Collections:Articles published by FPT lecturers

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